1. Technical Field
The present invention relates to a clock signal source that provides a precise programmable output frequency. More particularly, the present invention relates to the use of Direct Digital Synthesis (DDS) or “phase accumulation” to provide a clock source with a fine resolution and low jitter.
2. Related Art
If it is necessary to generate a programmable output frequency with fine resolution and low jitter, for example as a clock source for a digital circuit, there is a natural conflict between programmability and stability, i.e. between frequency granularity and jitter. DDS or “phase accumulation” is the well-known traditional method to perform this function.
For DDS, an accumulator is clocked by the IC system clock, and overflow of the accumulator provides a digital pulse. The frequency of the pulse is related to the input to the accumulator. To program the frequency of overflow from the accumulator, a user selects the number added in the accumulator each clock cycle.
DDS can generate an average frequency with high resolution, limited only by the length of the accumulator. When operating near the limits of the IC system clock, jitter will be up to (plus or minus) one half clock period of the accumulator clock frequency. This means that jitter is >1 ns, with an accumulator operating at a maximum IC system clock frequency of approximately 500 MHz. For many clocking applications, this jitter is unacceptable.
Traditional jitter reduction methods include use of a phase locked loop (PLL) and well as digital signal manipulation. A phase locked loop is an analog device. A digital alternative is provided on the Spartan 3 and Virtex 4 series of Field Programmable Gate Arrays (FPGAs) manufactured by Xilinx, Inc. of San Jose, Calif., which uses a digital clock manager in frequency lock mode. But this mode can introduce frequency wander, where the period itself has little jitter, but the concatenation of many slightly-too-long or slightly-too-short periods can generate large timing errors, which is unacceptable in communication applications.
It is, therefore, desirable to provide a jitter reduction method for an IC so that a programmable frequency output can be provided near the limits of the IC system clock with minimal jitter.